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mp specifications november 7, 2008 revision 1.0 u ltra c hip the coolest lcd driver, ever! 65x132 stn controller-driver h igh -v oltage m ixed -s ignal ic
uc1701 x 65x132 stn controller-drivers revision a1.0 2 table of content i ntroduction .................................................................................................................3 m ain a pplications .........................................................................................................3 f eature h ighlights .......................................................................................................3 o rdering i nformation ..................................................................................................4 b lock d iagram ..............................................................................................................5 p in d escription .............................................................................................................6 r ecommended cog l ayout ..........................................................................................9 c ontrol r egisters .....................................................................................................10 c ommand t able ...........................................................................................................12 c ommand d escription .................................................................................................13 lcd v oltage s etting ..................................................................................................18 v lcd q uick r eference .................................................................................................19 lcd d isplay c ontrols ...............................................................................................21 ito l ayout and lc s election ....................................................................................22 h ost i nterface ............................................................................................................25 d isplay d ata ram (ddram) ......................................................................................29 r eset & p ower m anagement ......................................................................................31 esd c onsideration .....................................................................................................36 a bsolute m aximum r atings ........................................................................................37 s pecifications .............................................................................................................38 ac c haracteristics ....................................................................................................39 p hysical d imensions ...................................................................................................43 a lignment m ark i nformation .....................................................................................44 p ad c oordinates .........................................................................................................45 t ray i nformation ........................................................................................................47 r evision h istory .........................................................................................................48
uc1701 x 65x132 stn controller-drivers revision a1.0 3 uc1701x single-chip, ultra-low power 65com by 132seg passive matrix lcd controller-driver i ntroduction uc1701x is an advanced high-voltage mixed- signal cmos ic, especially designed for the display needs of ultra-low power hand-held devices. this chip employs ultrachip?s unique dcc (direct capacitor coupling) driver architecture to achieve near crosstalk free images. in addition to low power column and row drivers, the ic contains all necessary circuits for high-v lcd power supply, bias voltage generation, timing generation and graphics data memory. advanced circuit design techniques are employed to minimize external component counts and reduce connector size while achieving extremely low power consumption. m ain a pplications ? cellular phones, smart phones, pda, and other battery operated palm top devices or portable instruments f eature h ighlights ? single chip controller-driver support 65x132 graphics stn lcd panels. ? support both row ordered and column ordered display buffer ram access. ? support industry standard 8-bit parallel bus (8080 or 6800 mode) and 4-wire serial bus (s8) interface. ? ultra-low power consumption under all display patterns. ? fully programmable mux rate and bias ratio allow many flexible power management options. ? 7-x internal charge pump with on-chip pumping capacitor requires only 3 external capacitors to operate. ? on-chip power-on reset and software reset commands, make rst pin optional. ? very low pin count (10-pin) allows exceptional image quality in cog format on conventional ito glass. ? flexible data addressing/mapping schemes to support wide ranges of software models and lcd layout placements. ? v dd range (typ.): 1.8v ~ 3.3v v dd2/3 range(typ.): 2.5v ~ 3.3v lcd v op range: 3.9v ~ 11.5v ? available in gold bump dies ? com/seg bump information bump pitch: 27 m bump gap: 12 m bump surface: 2077.5 m 2
u ltra c hip high-voltage mixed-signal ic ?1999~2008 4 mp specifications o rdering i nformation part number i 2 c description UC1701XGAA no gold bumped die general notes a pplication i nformation for improved readability, the specification contains many applic ation data points. when applicati on information is given, it is advisory and does not form part of the specification for the device. b are d ie d isclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of. there is no post waffle saw/pack testing performed on individual die. although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, ultrachip has no control of third party procedures in the handling, packing or assembly of the die. accordingly, it is the responsibility of the customer to test and qualify their application in which the d ie is to be used. ultrachip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. l ife s upport a pplications these devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. customer using or selling these products for use in such applications do so at their own risk. c ontent d isclaimer ultrachip believes the information contained in this document to be accurate and reliable. however, it is subject to change without notice. no responsibility is assumed by ultrachip for its use, nor for infringement of patents or other rights of third parties. no part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of ultrachip inc. ultrachip's terms and conditions of sale apply at all times. c ontact d etails ultrachip inc. (headquarter) 2f, no. 70, chowtze street, nei hu district, taipei 114, taiwan, r. o. c. tel: +886 (2) 8797-8947 fax: +886 (2) 8797-8910 sales e-mail: sales@ultrachip.com web site: http://www.ultrachip.com
uc1701 x 65x132 stn controller-drivers revision a1.0 5 b lock d iagram display data ram column address generator display data latches level shifters seg drivers data ram i/o buffer page address generator row address generator level shifter com drivers v lcd & bias generator host interface command control & status register clock & timing generator power on & reset control c b1 c b0 c l
u ltra c hip high-voltage mixed-signal ic ?1999~2008 6 mp specifications p in d escription name type pins description m ain p ower s upply v dd v dd2 v dd3 pwr 3 4 2 v dd supplies for display data ram and digital logic, v dd2 supplies for v lcd and v d generator, v dd3 supplies for v bias and other analog circuits. v dd2 /v dd3 should be connected to the same power source. but v dd can be connected to a source voltage no higher than v dd2 /v dd3 . please maintain the following relationship: v dd +1.3v v dd2/3 v dd ito trace resistance needs to be minimized for v dd2 /v dd3. v ss v ss2 gnd 2 4 ground. connect v ss and v ss2 to the shared gnd pin. in cog applications, minimize the ito resistance for both v ss and v ss2 . lcd p ower s upply & v oltage c ontrol v b0+ v b0? v b1+ v b1? pwr 2 2 4 2 lcd bias voltages. these are the voltage sources to provide seg driving currents. these voltages are generated internally. connect capacitors of c bx value between v bx+ and v bx? . in cog application, the resistance of these ito traces directly affects the seg driving strength of the resulting lcd module. minimize these trace resistance is critical in achieving high quality image. v lcdin v lcdout pwr 2 2 main lcd power supply. when v lcd is used, connect these pins together. by-pass capacitor c l is optional. it can be connected between v lcd and v ss . when c l is used, keep the ito trace resistance around 70~100 ? . n ote ? recommended capacitor values: c b : 2.2f/5v or 100~250x(lcd load capacitance). c l : 330nf/25v is appropriate for most applications.
uc1701 x 65x132 stn controller-drivers revision a1.0 7 name type pins description h ost i nterface bm0 bm1 i 1 1 bus mode: the interface bus mode is determined by bm[1:0] and {d7, d6} by the following relationship: bm[1:0] {d7, d6} mode 11 data 6800/8-bit 10 data 8080/8-bit 0x sda, sck 4-wire spi w/ 8-bit token (s8: conventional) cs0 i 1 chip select. chip is selected when cs0 = ?l?. when the chip is not selected, d[7:0] will be of high impedance. rst i 1 when rst=?l?, all control registers are re-initialized by their default states. since uc1701x has built-in power-on reset and software reset command, rst pin is not required for proper chip operation. an rc filter has been included on-chip. there is no need for external rc noise filter. when rst is not used, connect the pin to v dd . cd i 1 select control data or display data for read/write operation. ?l?: control data ?h?: display data wr0 wr1 i 1 1 wr [1:0] controls the read/write operation of the host interface. see host interface section for details. in parallel mode, the meaning of wr[1:0] depends on which interface it is in, 6800 or 8080 mode. in serial interface modes, these two pins are not used, connect them to v ss or v dd . dt1 dt2 i 1 1 duty selection. dt2 dt1 duty 0 0 1/65 0 1 1/49 1 0 1/33 1 1 1/55 d7~d0 i/o 8 bi-directional bus for both serial and parallel host interfaces. in serial modes, connect d[7] to sda, d[6] to sck. d7 d6 d5 d4 d3 d2 d1 d0 bm=1x (8-bit) db7 db6 db5 db4 db3 db2 db1 db0 bm=0x (s8) sda sck -- -- -- -- -- -- always connect unused pins to either v ss or v dd . h igh v oltage lcd d river o utput seg1 ~ seg132 hv 132 seg (column) driver outputs. support up to 132 pixels. leave unused seg drivers open-circuit. com1 ~ com64 hv 64 com (row) driver outputs. support up to 64 rows. when designing lcm, always start from com1. if the lcm has n pixel rows and n is less than 64, set cen to be n-1 , and leave com drivers [n+1 ~ 64] open-circuit. cic hv 2 icon driver outputs. leave it open if not used.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 8 mp specifications name type pins description m isc . p ins v ddx 4 auxiliary v dd . this pin is connected to the main v dd bus within the ic. it?s provided to facilitate chip configurations in cog application. there?s no need to connect v ddx to main v dd externally and it should not be used to provide v dd power to the chip. tst4 i 1 test control. there?s an on-chip pull-up resistor for tst4. leave it open during normal use. tst2 i/o 1 test i/o pins. leave these pins open during normal use. dummy 11 dummy pins are not connected inside the ic. note: several control registers will specify ?0 based index? for com and seg electrodes. in those situations, com x or seg x will correspond to index x -1, and the value range for those index register will be 0~63 for com and 0~131 for seg.
uc1701 x 65x132 stn controller-drivers revision a1.0 9 r ecommended cog l ayout com<54> com<55> com<56> com<57> com<58> com<59> com<60> com<61> com<62> com<63> com<64> cic tst4 cs0 rst cd wr0 wr1 vddx d0 d1 d2 d3 d4 d5 d6 d7 vdd1 vdd1 vdd2 vdd2 vdd2 vdd3 v ss1 v ss1 v ss2 v ss2 v ss2 v ss2 vb 1+ vb 1+ dummy vb 0+ vb 0+ vb0- vb0- dummy vb1- vb1- vb 1+ vb 1+ vlcdin vlcdin vlcdout vlcdout dummy dummy dummy dummy dummy dummy dummy dummy dummy tst2 vs sx vddx bm0 bm1 dt1 vs sx dt2 vdd1 vdd2 vdd3 com<32> com<31> com<30> com<29> com<28> com<27> com<26> com<25> com<24> com<23> com<22> com<21> com<20> com<19> com<18> com<17> com<16> com<15> com<14> com<13> com<12> com<11> com<10> com<9> com<8> com<7> com<6> com<5> com<4> com<3> com<2> com<1> cic seg<1> seg<2> seg<3> seg<4> seg<5> seg<6> seg<7> seg<8> seg<9> seg<10> seg<11> seg<12> seg<13> seg<14> seg<15> seg<16> seg<17> seg<18> seg<19> seg<20> seg<21> seg<22> seg<23> seg<24> seg<25> seg<26> seg<27> seg<28> seg<29> seg<30> seg<31> seg<32> seg<33> seg<34> seg<35> seg<36> seg<37> seg<38> seg<39> seg<40> seg<41> seg<42> seg<43> seg<44> seg<45> seg<46> seg<47> seg<48> seg<49> seg<50> seg<51> seg<52> seg<53> seg<54> seg<55> seg<56> seg<57> seg<58> seg<59> seg<60> seg<61> seg<62> seg<63> seg<64> seg<65> seg<66> seg<67> seg<68> seg<69> seg<70> seg<71> seg<72> seg<73> seg<74> seg<75> seg<76> seg<77> seg<78> seg<79> seg<80> seg<81> seg<82> seg<83> seg<84> seg<85> seg<86> seg<87> seg<88> seg<89> seg<90> seg<91> seg<92> seg<93> seg<94> seg<95> seg<96> seg<97> seg<98> seg<99> seg<1 00> seg<1 01> seg<1 02> seg<1 03> seg<1 04> seg<1 05> seg<1 06> seg<1 07> seg<1 08> seg<1 09> seg<1 10> seg<1 11> seg<1 12> seg<1 13> seg<1 14> seg<1 15> seg<1 16> seg<1 17> seg<1 18> seg<1 19> seg<1 20> seg<1 21> seg<1 22> seg<1 23> seg<1 24> seg<1 25> seg<1 26> seg<1 27> seg<1 28> seg<1 29> seg<1 30> seg<1 31> seg<1 32> com<33> com<34> com<35> com<36> com<37> com<38> com<39> com<40> com<41> com<42> com<43> com<44> com<45> com<46> com<47> com<48> com<49> com<50> com<51> com<52> com<53> uc1701x bump view cs0 rst cd wr0 wr1 d0 d1 d2 d3 d4 d5 d6 d7 vdd vss vb1+ vb0+ vb0- vb1- vlcdin vlcdout bm0 bm1 dt1 dt2 vb1- vb1- n otes for v dd with cog: the operation condition, v dd =1.8v (typical), should be satisfied under all operating conditions. uc1701x?s peak current (i dd ) can be up to ~15ma during high speed data-write to uc1701x?s on-chip sram. such high pulsing current mandates very careful design of v dd and v ss ito trances in cog modules. when v dd and v ss trace resistance is not low enough, the pulsing i dd current can cause the actual on-chip v dd to drop to below 1.65v and cause the ic to malfunction.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 10 mp specifications c ontrol r egisters uc1701x contains registers, which control the chip operation. the following table is a summary of these control registers, a brief description and the default values. these registers can be modified by commands, which will be described in the next two sections, command table and command description. name: the symbolic reference of the register. note that, some symbol name refers to bits (flags) within another register. default: numbers shown in bold font are default values after power-up-reset and system-reset . name bits default description sl 6 00h scroll line. scroll the displayed image up by sl rows. the valid sl value is between 0 (for no scrolling) and 63. setting sl outside of this range causes undefined effects on the displayed image. this register does not affect icon output cic. ca 8 00h column address of ddram (displ ay data ram). value range is 0~131. (used in host to access ddram) pa 4 0h page address of ddram. value range 0~8. (used in host to access ddram) br 1 0h bias ratio. the ratio between v lcd and v bias varies according to duty selected: br=0 br=1 duty=1/65 1/9 1/7 duty=1/49 1/8 1/6 duty=1/33 1/6 1/5 duty=1/55 1/8 1/6 pm 6 20h adjust contrast of lcd panel display. pc 6 20h power control. pc [0] : voltage follower. (default 0: off ) pc [1] : voltage regular. (default 0: off ) pc [2] : booster ratio. (default 0: off ) pc [5:3]: resistor ratio for v lcd . (default 100b ) 000b~111b : rb/ra ratio setting cr 8 0h return column address. useful for cursor implementation. ac3 1 0h address control. ac3: cum: cursor update mode, (default 0: off ) when cum=1, ca increment on write only, wrap around suspended dc 3 0h display control: dc[0]: pxv: pixels inverse (bit-wise data inversion. default 0: off ) dc[1]: apo: all pixels on (default 0: off ) dc[2]: display on/off (default 0: off ) when dc[2] is set to 0, the ic will enter sleep mode lc 2 0h lcd control: lc[0]: mx, mirror x seg/column sequence inversion (default: off ) lc[1]: my, mirror y com/row sequence inversion (default: off )
uc1701 x 65x132 stn controller-drivers revision a1.0 11 name bits default description apc0 apc1 8 8 90h -- advanced program control. for ultrachip only. do not use. apc0 [7] : tc, v bias temperature compensation coefficient (%-per- o c) 0b : tc curve definition = -0.05% / o c 1b : tc curve definition = -0.11% / o c apc0 [1:0] : wa, automatic column/row wrap around. wa[0] : 0: pa wrap around disable 1: pa wrap around enable. wa[1] : 0: ca wrap around disable 1: ca wrap around enable. apc1[7:0] : for ultrachip?s use only. status registers bz, mx, de, rst 1 0 bz : set to 1 when system is busy. commands can only be accepted when bz=0. mx : mirror x-axle (i.e. seg or column) de : set to 1 when display enabled. rst : reset flag. rst=1 when reset is in progress.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 12 mp specifications c ommand t able the following is a list of host commands supported by uc1701x c/d: 0: control, 1: data w/r: 0: write cycle, 1: read cycle # useful data bits ? don?t care command c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 action default 1. write data byte 1 0 ######## write 1 byte n/a 2. read data byte 1 1 ######## r ead 1 byte n/a 3. get status 0 1 bz mx de rst 0000 get status -- set column address lsb 0000#### set ca [3:0] 0 4. set column address msb 0 0 0001#### set ca [7:4] 0 5. set power control 0 0 00101### set pc[2:0] 000b 6. set scroll line 0 0 01###### set sl[5:0] 0 7. set page address 0 0 1011#### set pa[3:0] 0 8. set v lcd resistor ratio 0 0 00100### set pc[5:3] 100b 10000001 9. set electronic volume (double-byte command) 0 0 00###### set pm[5:0] 20h 10. set all-pixel-on 0 0 1010010# set dc[1] 0b 11. set inverse display 0 0 1010011# set dc[0] 0b 12. set display enable 0 0 1010111# set dc[2] 0b 13. set seg direction 0 0 1010000# set lc[0] 0b 14. set com direction 0 0 1100# - - - set lc[1] 0b 15. system reset 0 0 11100010 system reset n/a 16. nop 0 0 11100011 no operation n/a 17. set lcd bias ratio 0 0 1010001# set br 0b 18. set cursor update mode 0 0 11100000ac3=1, cr=ca n/a 19. reset cursor update mode 0 0 11101110ac3=0, ca=cr. n/a 20. set static indicator off 0 0 10101100 nop n/a set static indicator on 10101101 21. set static indicator 0 0 -------- nop n/a 11111000 22. set booster ratio (double-byte command) 0 0 000000## nop 00b 23. set power save (compound command) 0 0 ######## display off & all pixel on n/a 111111 tt 24. set test control (double-byte command) 0 0 - ####### for uci only do not use n/a 11111010 25. set adv. program control 0 (double-byte command) 0 0 #00100## set tc, wa[1:0] 90h 11111011 26. set adv. program control 1 (double-byte command) 0 0 ######## for uci only set apc1 n/a * other than commands listed above, all other bit patterns result in nop (no operation).
uc1701 x 65x132 stn controller-drivers revision a1.0 13 c ommand d escription 1. write data byte to memory action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 write data 1 0 8-bit data write to sram 2. read data byte from memory action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 read data 1 1 8-bit data read from sram write/read data byte (command 1,2) access display data ram based on page address (pa) register and column address (ca) register. pa and ca can also be programmed directly by issuing set page address and set column address commands. 3. get status action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 get status 0 1 bz mx de rst 000 0 bz: bz=1 when busy. the system accepts commands only when bz=0. mx : mirror x. status of register lc[0] de : display enable flag. de=1 when display is enabled. rst : rst flag. rst=1 when reset is in progress. 4. set column address action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set column address lsb, ca[3:0] 0 0 0000 ca3 ca2 ca1 ca0 set column address msb, ca[7:4] 0 0 0001 ca7 ca6 ca5 ca4 set the sram column address before write/read memory from host interface. ca value range: 0~131 5. set power control action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set power control, pc[2:0] 0 0 00101 pc2 pc1 pc0 set pc[2:0] to enable the built-in charge pump. pc[2] : 0 ? boost off 1 ? boost on pc[1] : 0 ? voltage regular off 1 ? voltage regular on pc[0] : 0 ? voltage follower off 1 ? voltage follower on
u ltra c hip high-voltage mixed-signal ic ?1999~2008 14 mp specifications 6. set scroll line action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set scroll line, sl[5:0] 0 0 01 sl5 sl4 sl3 sl2 sl1 sl0 set the scroll line number. range : 0~63 scroll line setting will scroll the displayed image up by sl rows. icon output cic will not be affected by set scroll line command. image row 0 : image row n-1 image row n : : image row 63 row 0 : : row 63 image row n : : image row 63 image row 0 : image row n-1 row 0 : : row 63 sl=0 sl=n 7. set page address action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set page address, pa[3:0] 0 0 1011 pa3 pa2 pa1 pa0 set the sram page address before write/read memory from host interface. each page of sram corresponds to 8 com lines on lcd panel, except for the last page. the last page corresponds to the icon output cic. possible value = 0~8. 8. set v lcd resistor ratio action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set v lcd resistor ratio, pc[5:3] 0 0 00100 pc5 pc4 pc3 configure pc[5:3] to set internal resistor ratio, rb/ra, for the v lcd voltage regulator to adjust the contrast of the display panel: pc[5:3] : 000b~111b ? 1+rb/ra ratio. default : 100b. refer to v lcd quick reference for ?1+rb/ra? ratio. v lcd =((1+rb/ra) x vev) x (1+(t-25)xc t %) vev=(1-(63-pm)/162)xv ref where rb and ra are internal resistors, v ref is on-chip contrast voltage, and pm is a vaule of electronic volume 9. set electronic volume action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 1000000 1 set electronic volume, pm[5:0] 0 0 00 pm5 pm4 pm3 pm2 pm1 pm0 set pm[5:0] for electronic volume ?pm? for vlcd voltage regulator to adjust contrast of lcd panel display effective range : 0~63. default : 32
uc1701 x 65x132 stn controller-drivers revision a1.0 15 10. set all pixel on action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set all pixel on, dc [1] 0 0 1010010 dc1 set dc[1] to force all seg drivers to output on signals. this function has no effect on the existing data stored in display ram. default : 0 11. set inverse display action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set inverse display, dc [0] 0 0 1010011 dc0 set dc[0] to force all seg drivers to output the inverse of the data (bit-wise) stored in display ram. this function has no effect on the existing data stored in display ram. 12. set display enable action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set display enable, dc[2] 0 0 1010111 dc2 this command is for programming register dc[2]. when dc[2] is set to 1, uc1701x will first exit from sleep mode, restore the power and then turn on com drivers and seg drivers. 13. set seg direction action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set segment direction, lc[0] 0 0 1010000 mx set lc[0] for seg (column) mirror (mx). default : 0 mx is implemented by reversing the mapping order between ram and seg (column) electrodes. the data stored in ram is not affected by mx command. yet, mx has immediate effect on the display image. 14. set com direction action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set common direction, lc[1] 0 0 1100 my -- - set lc[1] for com (row) mirror (my). my is implemented by reversing the mapping between ram and com (row) electrodes. the data stored in ram is not affected by my command. yet, my has immediate effect on the display image. 15. system reset action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 system reset 0 0 1110001 0 this command will activate the system reset. control register values will be reset to their default values. data store in ram will not be affected. 16. nop action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 no operation 0 0 1110001 1 this command is used for ?no operation?.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 16 mp specifications 17. set lcd bias ratio action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set bias ratio, br 0 0 1010001 br select voltage bias ratio required for lcd. default : 0 the setting of bias ratio varies according to duty: duty br = 0 br = 1 1/65 1/9 1/7 1/49 1/8 1/6 1/33 1/6 1/5 1/55 1/8 1/6 18. set cursor update mode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set cursor update mode 0 0 1110000 0 this command is used for set cursor update mode function. when cursor update mode sets, uc1701x will update register cr with the value of register ca. the column address ca will increment with write ram data operation but the address wraps around will be suspended no matter what wa setting is. however, the column address will not increment in read ram data operation. the set cursor update mode can be used to implement ?write after read ram? function. the column address (ca) will be restored to the value, which is before the set cursor update mode command, when reset cursor update mode. the purpose of this pair commands and their feature is to support ?write after read? function for cursor implementation. 19. reset cursor update mode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 reset cursor update mode 0 0 1110111 0 set ac3=0 and ca=cr. 20. set static indicator off action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 turn off static indicator 0 0 1010110 0 no operation. 21. set static indicator on action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1010110 1 turn on static indicator 00 - - - - - - - - no operation.
uc1701 x 65x132 stn controller-drivers revision a1.0 17 22. set booster ratio action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 0 0 0 set booster ratio (double-byte command) 01 0000 00 - - this command is used for ?no operation?. 23. set power save action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 power save (compound command) 00 ####### # 24. set test control action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 111111 tt set tt (double-byte command) 01 - # # # # # # # this command is for ultrachip?s test only. do not use. 25. set advanced program control 0 action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 1111101 0 set adv. program control, apc0 [7:0] (double-byte command) 00 tc 00100 wa1 wa0 tc : apc0 [7], v bias temperature compensation coefficient (%-per-degree-c) temperature compensation curve definition: tc : 0b = -0.05%/ o c, 1b = -0.11%/ o c wa : apc0 [1:0], automatic column/row wrap around. wa[0] : 0: pa wa disable 1: pa wa enable. wa[1] : 0: ca wa disable 1: ca wa enable. 26. set advanced program control 1 action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 1111101 1 set adv. program control, apc1 [7:0] (double-byte command) 00 apc1 register parameter for ultrachip only. please do not use.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 18 mp specifications lcd v oltage s etting m ultiplex r ates multiplex rate is completely software programmable in uc1701x via registers cen, dst, den, and partial display control flags lc[4]. combined with low power partial display mode and a low bias ratio of 6, uc1701x can support wide variety of display control options. for example, when a system goes into stand-by mode, a large portion of lcd screen can be turned off to conserve power. b ias r atio s election bias ratio ( br ) is defined as the ratio between v lcd and v bias , i.e. br = v lcd /v bias , where v bias = v b1+ ? v b1? = v b0+ ? v b0? . the theoretical optimum bias ratio can be estimated by 1 + mux . br of value 15~20% lower/higher than the optimum value calculated above will not cause significant visible change in image quality. uc1701x supports four br as listed below. br can be selected by software program. bias ratio duty br=0 br=1 1/65 1/9 1/7 1/49 1/8 1/6 1/33 1/6 1/5 1/55 1/8 1/6 table 1: bias ratios t emperature c ompensation the temperature compensation coefficients is ?0.11% per o c. v lcd g eneration v lcd is supplied by internal charge pump. the source of v lcd is controlled by pc[2:0]. for good product reliability, it is recommended to keep v lcd under 11.5v for all temperature conditions. when v lcd is generated internally, the voltage level of v lcd is determined by three control registers: br (bias ratio), pm (potentiometer), and pc[5:3] (v lcd resistor ratio) with the following relationship: v lcd =((1+rb/ra) x vev) x (1+(t-25)xc t %) vev=(1-(63-pm)/162)xv ref where ra and rb are two design constants, whose value depends on the setting of br register, as illustrated in the table on the next page, pm is value of electronic volume, v reg is on-chip contrast voltage, t is the ambient temperature in o c, and c t is temperature compensation coefficient. v lcd f ine t uning black-and-white stn lcd is sensitive to even a 1% mismatch between ic driving voltage and the v op of lcd. however, it is difficult for lcd makers to guarantee such high precision matching of parts from different venders. it is therefore necessary to adjust v lcd to match the actual v op of the lcd. for the best result, software based approach for v lcd adjustment is the recommended method for v lcd fine-tuning. system designers should always consider the contrast fine tuning requirement before finalizing on the lem design l oad d riving s trength the power supply circuit of uc1701x is designed to handle lcd panels with loading up to ~24nf using 20- ? /sq ito glass with v dd2/3 2.4v. for larger lcd panels, use lower resistance ito glass packaging.
uc1701 x 65x132 stn controller-drivers revision a1.0 19 v lcd q uick r eference 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 0 4 8 12162024283236404448525660 pm vlcd v lcd programming curve. pc[5:3] 1+rb/ra v ref pm v lcd range (v) 0 3.87 000b 3.769 1.68 63 6.33 0 4.51 001b 4.396 1.68 63 7.38 0 5.15 010b 5.020 1.68 63 8.43 0 5.79 011b 5.643 1.68 63 9.48 0 6.43 100b 6.266 1.68 63 10.53 0 7.08 101b 6.891 1.68 62 11.51 0 7.72 110b 7.517 1.68 48 11.46 0 8.36 111b 8.143 1.68 37 11.48 note: for good product reliability, keep v lcd under 11.5v over all temperature.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 20 mp specifications h i - v g enerator and bias reference circuit cl vdd2/vdd3 uc1701 (optional) vlcdout cb1 vdd2 vdd vb1- cb0 vdd rl vss2 vdd3 vss vb1+ vb0- vb0+ vlcdin f igure 1: reference circuit using internal hi-v generator circuit note sample component values: (the illustrated circuit and component values are for reference only. please optimize for specific requirements of each application.) c bx : 2.2 f/5v or 100~250x lcd load capacitance. c l : 330nf(25v) is appropriate for most applications. r l : 3.3m~10m ? to act as a draining circuit when v dd is shut down abruptly .
uc1701 x 65x132 stn controller-drivers revision a1.0 21 lcd d isplay c ontrols c lock & t iming g enerator uc1701x contains a built-in system clock. all required components for the clock oscillator are built-in. no external parts are required. 4 different frame rates are provided based on different mux-rate for system design flexibility. d river m odes com and seg drivers can be in either idle mode or active mode, controlled by display enable flag (dc[2]). when seg and com drivers are in idle mode, they will be connected together to ensure zero dc condition on the lcd. d river a rrangements the naming conventions are: com x, where x = 1~64, refers to the row driver for the x-th row of pixels on the lcd panel. the mapping of com(x) to lcd pixel rows is fixed and it is not affected by sl, mx or my settings. d isplay c ontrols there are three groups of display control flags in the control register dc: driver enable (de), all- pixel-on (apo) and inverse (pxv). de has the overriding effect over pxv and apo. d river e nable (de) driver enable is controlled by the value of dc[2] via set display enable command. when dc[2] is set to off (logic ?0?), both com and seg drivers will become idle and uc1701x will put itself into sleep mode to conserve power. when dc[2] is set to on, the de flag will become ?1?,and uc1701x will first exit from sleep mode, restore the power (v lcd , v d etc.) and then turn on com and seg drivers. a ll p ixels o n (apo) when set, this flag will force all seg drivers to output on signals, disregarding the data stored in the display buffer. this flag has no effect when display enable is off and it has no effect on data stored in ram. i nverse (pxv) when this flag set to on, seg drivers will output the inverse of the value it received from the display buffer ram (bit-wise inversion). this flag has no impact on data stored in ram.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 22 mp specifications ito l ayout and lc s election since com scanning pulses of uc1701x can be as short as 153s, it is critical to control the rc delay of com and seg signal to minimize crosstalk and maintain good mass production consistency. com t races excessive com scanning pulse rc decay can cause fluctuation of contrast and increase com direction crosstalk. please limit the worst case of com signals rc delay (rc max ) as calculated below (r row / 2.7 + r com ) x c row < 9.23 s where c row : lcd loading capacitance of one row of pixels. it can be calculated by c lcd /mux- rate, where c lcd is the lcd panel capacitance. r row : ito resistance over one row of pixels within the active area r com : com routing resistance from ic to the active area + com driver output impedance. in addition, please limit the min-max spread of rc decay to be: | rc max ? rc min | < 2.76 s so that the com distortions on the top of the screen to the bottom of the screen are uniform. (use worst case values for all calculations) seg t races excessive seg signal rc decay can cause image dependent changes of medium gray shades and sharply increase the crosstalk of seg direction. for good image quality, please minimize seg ito trace resistance and limit the worst case of seg signal rc delay as calculated below. (r col / 2.7 + r seg ) x c col < 6.30 s where c col : lcd loading capacitance of one pixel column. it can be calculated by c lcd / (# of column), where c lcd is the lcd panel capacitance. r col : ito resistance over one column of pixels within the active area r seg : seg routing resistance from ic to the active area + seg driver output impedance. (use worst case values for all calculations) s electing l iquid c rystal the selection of lc material is crucial to achieve the optimum image quality of finished lcm. when (v 90 -v 10 )/v 10 is too large, image contrast will deteriorate, and images will look murky and dull. when (v 90 -v 10 )/v 10 is too small, image contrast will become too strong, and crosstalk will increase. for the best result, it is recommended the lc material has the following characteristics: (v 90 -v 10 )/v 10 = (v on -v off )/v off x 0.72~0.80 where v 90 and v 10 are the lc characteristics, and v on and v off are the on and off v rms voltage produced by lcd driver ic at the specific mux-rate. example: duty bias v on /v off -1 x0.80 x0.72 1/65 1/9 10.6% 9.6% 7.5%
uc1701 x 65x132 stn controller-drivers revision a1.0 23 f igure 2: com and seg electrode driving waveform ram w/r pol com1 com2 com3 seg1 seg2
u ltra c hip high-voltage mixed-signal ic ?1999~2008 24 mp specifications t he c ommon o utput s tatus s elect c ircuit in the uc1701x chips, the com output scan direction can be selected by the common output status select command. (see the table below for details.) consequently, the constraints in ic layout at the time of lcd module assembly can be minimized. duty direction com[1:16] com [17:24] com [25:27] com [28:37] com [38:40] com [41:48] com[49:64] coms 0 com [1:64] 1/65 1 com [64:1] coms 0 com[1:24] nc com [25:48] 1/49 1 com[48:25] nc com [24:1] coms 0 com[1:16] nc com[17:32] 1/33 1 com[32:17] nc com[16:1] coms 0 com [1:27] nc com [28:54] 1/55 1 com [54:28] nc com [27:1] coms table 2: duty layout
uc1701 x 65x132 stn controller-drivers revision a1.0 25 h ost i nterface as summarized in the table below, uc1701x supports two 8-bit parallel bus protocols and one serial bus protocol. designers can choose either the 8-bit parallel bus to achieve high data transfer rate, or use serial bus to create compact lcd modules and minimize connector pins. bus type 8080 6800 s8 (4-wire) width 8-bit 8-bit serial access read / write write only bm[1:0] 10 11 00 cs0 chip select cd control/data wr0 ___ __ wr _ _ r/w ? wr1 ___ __ rd en ? db[5:0] data ? control & data pins db[7:6] data db[6]=sck, db[7]=sda * connect unused control pins and data bus pins to v dd or v ss cs disable bus interface cs init. bus state reset init. bus state 8-bit 9 ? 9 s8 9 9 9 ? cs disable bus interface ? cs can be used to disable bus interface write / read access. ? reset can be pin reset / soft reset / power on reset. table 3: host interfaces summary
u ltra c hip high-voltage mixed-signal ic ?1999~2008 26 mp specifications p arallel i nterface the timing relationship between uc1701x internal control signal rd, wr and their associated bus actions are shown in the figure below. the display ram read interface is implemented as a two-stage pipeline. this architecture requires that, every time memory address is modified, either in parallel mode or serial mode, by either set ca or set pa command, a dummy read cycle need to be performed before the actual data can propagate through the pipeline and be read from data port d[7:0]. there is no pipeline in write interface of display ram. data is transferred directly from bus buffer to internal ram on the rising edges of write pulses. l lsb d l d l+k c msb c lsb dummy d c d c+1 m msb m lsb l l+k l+k+1 c c+1 c+2 c+3 m d l d l+k dummy d c d c+1 d c+2 external cd ___ wr __ rd d[7:0] internal write read data latch column address figure 3: parallel interface & related internal signals s erial i nterface uc1701x supports 1 serial modes: 4-wire spi mode (s8). bus interface mode is determined by the wiring of the bm[1:0]. see table in last page for more detail. s8 (4- wire ) i nterface only write operations are supported in 4-wire serial mode. pin cs[1:0] are used for chip select and bus cycle reset. pin cd is used to determine the content of the data been transferred. during each write cycle, 8 bits of data, msb first, are latched on eight rising sck edges into an 8-bit data holder. if cd=0, the data byte will be decoded as command. if cd=1, this 8-bit will be treated as data and transferred to proper address in the display data ram on the rising edge of the last sck pulse. pin cd is examined when sck is pulled low for the lsb (d0) of each token. cs0 sdi sck cd d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 figure 4: 4-wire serial interface (s8)
uc1701 x 65x132 stn controller-drivers revision a1.0 27 h ost interface reference circuit vdd mpu vdd cs0 cd d7~d0 vcc uc1701 wr0(wr) rd address wr rst bm1 gnd vdd bm0 vdd d7~d0 vss wr1(rd) decoder cd iorq f igure 5: 8080/8bit parallel mode reference circuit vdd mpu vcc wr0(r/w) rst uc1701 address r/w d7~d0 cd vss d7~d0 vdd iorq cs0 e gnd vdd decoder bm0 bm1 cd vdd wr1(e) f igure 6: 6800/8bit parallel mode reference circuit
u ltra c hip high-voltage mixed-signal ic ?1999~2008 28 mp specifications vcc vdd bm1 sda uc1701 wr1 sck sck(d6) mpu sda(d7) gnd cd iorq bm0 vss rst vdd d5~d0 d5~d0 cs0 wr0 vdd address decoder cd f igure 7: serial-8 serial mode reference circuit note ? the id pins are for production control. the connection will affect the content of d[7] of the 1st byte of the get status command. connect to v dd for ?h? or v ss for ?l?. ? rst pin is optional. when the rst pin is not used, connect it to v dd . ? when using i 2 c serial mode, cs1/0 are user configurable and affect a[3:2] of device address. ? r1, r2: 2k ~ 10k ? , use lower resistor for bus speed up to 3.6mhz, use higher resistor for lower power.
uc1701 x 65x132 stn controller-drivers revision a1.0 29 d isplay d ata ram (ddram) d ata o rganization the input display data is stored to a dual port static ddram (ddram, for display data ram) organized as 65x132. after setting ca and ra, the subsequent data write cycle will store the data for the specified pixel to the proper memory location. please refer to the map in the following page between the relation of com, seg, sram, and various memory control registers. d isplay d ata ram a ccess the display ram is a special purpose dual port ram which allows asynchronous access to both its column and row data. thus, ram can be independently accessed both for host interface and for display operations. d isplay d ata ram a ddressing a host interface (hi) memory access operation starts with specifying row address (ra) and column address (ca) by issuing set row address and set column address commands. mx i mplementation column mirroring (mx) is implemented by selecting either (ca) or (131?ca) as the ram column address. changing mx affects the data written to the ram. since mx has no effect of the data already stored in ram, changing mx does not have immediate effect on the displayed pattern. to refresh the display, refresh the data stored in ram after setting mx. r ow m apping com electrode scanning orders are not affected by start line (sl), fixed line (flt & flb) or mirror y (my, lc[3]). visually, register sl having a non-zero value is equivalent to scrolling the lcd display up or down (depends on my) by sl rows. ram a ddress g eneration the mapping of the data stored in the display sram and the scanning electrodes can be obtained by combining the fixed r m scanning sequence and the following ram address generation formula. during the display operation, the ram line address generation can be mathematically represented as following: for the 1st line period of each field line = sl otherwise line = mod( line +1, 64) where mod is the modular operator, and line is the bit slice line address of ram to be outputted to column drivers. line 0 corresponds to the first bit-slice of data in ram. the above line generation formula produce the ?loop around? effect as it effectively resets line to 0 when line+1 reaches 64 . my i mplementation row mirroring (my) is implemented by reversing the mapping order between row electrodes and ram, i.e. the mathematical address generation formula becomes: for the 1 st line period of each field line = mod( sl + mr -1 , 64 ) otherwise line = mod( line-1 , 64 ) visually, the effect of my is equivalent to flipping the display upside down. the data stored in display ram is not affected by my.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 30 mp specifications line pa[3:0] 0 a ddecss sl=0 sl=16 sl=0 sl=0 sl=25 sl=25 d0 00h c1 c49 c64 c48 c25 c9 d1 01h c2 c50 c63 c47 c24 c8 d2 02h c3 c51 c62 c46 c23 c7 d3 03h c4 c52 c61 c45 c22 c6 d4 04h c5 c53 c60 c44 c21 c5 d5 05h c6 c54 c59 c43 c20 c4 d6 06h c7 c55 c58 c42 c19 c3 d7 07h c8 c56 c57 c41 c18 c2 d0 08h c9 c57 c56 c40 c17 c1 d1 09h c10c58c55c39c16 --- d2 0ah c11c59c54c38c15 --- d3 0bh c12c60c53c37c14 --- d4 0ch c13c61c52c36c13 --- d5 0dh c14c62c51c35c12 --- d6 0eh c15c63c50c34c11 --- d7 0fh c16c64c49c33c10 --- d0 10h c17 c1 c48 c32 c9 --- d1 11h c18 c2 c47 c31 c8 --- d2 12h c19 c3 c46 c30 c7 --- d3 13h c20 c4 c45 c29 c6 --- d4 14h c21 c5 c44 c28 c5 --- d5 15h c22 c6 c43 c27 c4 --- d6 16h c23 c7 c42 c26 c3 --- d7 17h c24 c8 c41 c25 c2 --- d0 18h c25 c9 c40 c24 c1 --- d1 19h c26 c10 c39 c23 c64 c48* d2 1ah c27 c11 c38 c22 c63 c47 d3 1bh c28 c12 c37 c21 c62 c46 d4 1ch c29 c13 c36 c20 c61 c45 d5 1dh c30 c14 c35 c19 c60 c44 d6 1eh c31 c15 c34 c18 c59 c43 d7 1fh c32 c16 c33 c17 c58 c42 d0 20h c33 c17 c32 c16 c57 c41 d1 21h c34 c18 c31 c15 c56 c40 d2 22h c35 c19 c30 c14 c55 c39 d3 23h c36 c20 c29 c13 c54 c38 d4 24h c37 c21 c28 c12 c53 c37 d5 25h c38 c22 c27 c11 c52 c36 d6 26h c39 c23 c26 c10 c51 c35 d7 27h c40 c24 c25 c9 c50 c34 d0 28h c41 c25 c24 c8 c49 c33 d1 29h c42 c26 c23 c7 c48 c32 d2 2ah c43 c27 c22 c6 c47 c31 d3 2bh c44 c28 c21 c5 c46 c30 d4 2ch c45 c29 c20 c4 c45 c29 d5 2dh c46 c30 c19 c3 c44 c28 d6 2eh c47 c31 c18 c2 c43 c27 d7 2fh c48 c32 c17 c1 c42 c26 d0 30h c49 c33 c16 --- c41 c25 d1 31h c50 c34 c15 --- c40 c24 d2 32h c51 c35 c14 --- c39 c23 d3 33h c52 c36 c13 --- c38 c22 d4 34h c53 c37 c12 --- c37 c21 d5 35h c54 c38 c11 --- c36 c20 d6 36h c55 c39 c10 --- c35 c19 d7 37h c56 c40 c9 --- c34 c18 d0 38h c57 c41 c8 --- c33 c17 d1 39h c58 c42 c7 --- c32 c16 d2 3ah c59 c43 c6 --- c31 c15 d3 3bh c60 c44 c5 --- c30 c14 d4 3ch c61 c45 c4 --- c29 c13 d5 3dh c62 c46 c3 --- c28 c12 d6 3eh c63 c47 c2 --- c27 c11 d7 3fh c64 c48 c1 --- c26 c10 1000 d0 40h page 8 cic cic cic cic cic cic 65 49 65 49 0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg128 seg129 seg130 seg131 seg132 1 seg132 seg131 seg130 seg129 seg128 seg127 seg126 seg125 seg5 seg4 seg3 seg2 seg1 mx 0110 0000 my=1 page 7 page 6 my=0 page 4 page 5 mux page 0 page 1 page 2 page 3 0111 0001 0010 0011 0100 0101 example for memory mapping: let mx = 0, my = 0, sl = 0, according to the data shown in the above table: ? page 0 seg 1 (d7-d0) : 11100000b ? page 0 seg 2 (d7-d0) : 00110011b
uc1701 x 65x132 stn controller-drivers revision a1.0 31 r eset & p ower m anagement t ypes of r eset uc1701x has two different types of reset: power-on-reset and system-reset . power-on-reset is performed right after v dd is connected to power. power-on-reset will first wait for about ~5ms, depending on the time required for v dd to stabilize, and then trigger the system reset . system reset can also be activated by software command or by connecting rst pin to ground. in the following discussions, reset means system reset . the differences between hardware reset and software reset are procedure hardware reset software reset display off: dc[2]=0, all segs/coms output at v ss v x normal display: dc[0]=0, dc[1]=0 v x seg normal direction: mx=0 v x clear serial counter and shift register (if using serial interface) v x bias selection: br=0 v x booster level bl[1:0]=0 v x exit power saving mode v x power control off: pc[2:0]=000b v x exit cursor update mode v v scroll line sl[5:0]=0 v v column address ca[7:0]=0 v v page address pa[3:0]=0 v v com normal direction: my=0 v v v lcd regulation ratio pc[5:3]=100b v v pm[5:0]=10 0000b v v exit test mode v v r eset s tatus when uc1701x enters reset sequence: ? operation mode will be ?reset? ? all control registers are reset to default values. refer to control registers for details of their default values. o peration m odes uc1701x has three operating modes (om): reset, sleep, normal. for each mode, the related statuses are as below: mode reset sleep normal om 00 10 11 host interface active active active clock off off on lcd drivers off off on charge pump off off on draining circuit on on off table 4: operating modes
u ltra c hip high-voltage mixed-signal ic ?1999~2008 32 mp specifications c hanging o peration m ode in addition to power-on-reset, two commands will initiate om transitions: set display enable , and system reset . when dc[2] is modified by set display enable , om will be updated automatically. there is no other action required to enter power saving mode. for maximum energy utilization, sleep mode is designed to retain charges stored in external capacitors c b0 , c b1 , and c l . to drain these capacitors, use reset command to activate the on-chip draining circuit.. action mode om reset command rst_ pin pulled ?l? power on reset reset 00 set driver enable to ?0? sleep 10 set driver enable to ?1? normal 11 table 5: om changes even though uc1701x consumes very little energy in sleep mode (typically under 2 a); however, since all capacitors are still charged, the leakage through com drivers may damage the lcd over the long term. it is therefore recommended to use sleep mode only for brief display off operations, such as full-frame screen updates, and to use reset for extended screen off operations. e xiting s leep m ode uc1701x contains internal logic to check whether v lcd and v bias are ready before releasing com and seg drivers from their idle states. when exiting sleep or reset mode, com and seg drivers will not be activated until uc1701x internal voltage sources are restored to their proper values.
uc1701 x 65x132 stn controller-drivers revision a1.0 33 p ower -u p s equence uc1701x power-up sequence is simplified by built-in ?power ready? flags and by the automatic invocation of system-reset command after power-on-reset . system programmer is required to wait for only 5 ~ 10 ms before starting to issue commands to uc1701x. no additional commands or waits are required between enabling of the charge pump, turning on the display drivers, writing to ram or any other commands. there?s no delay needed while turning on v dd and v dd2/3 , and either one can be turned on first. f igure 8: reference power-up sequence e nter /e xit s leep m ode s equence uc1503t enters sleep mode from display mode by issuing set display disable command and setting all-pixel-on. to exit sleep mode, set all-pixel-off. f igure 6: reference enter/exit sleep mode sequence sleep mode set dis p la y enable ( afh ) set display off (aeh) set all-pixel-on (a5h) set all-pixel-off (a4h) display mode display mode wait 5 ms wait 1 ms set rst low set rst high (issue commands) turn on the power wait for mtp-read 120ms set lcd bias ratio (br) set electronic volume (pm) set display enable (afh)
u ltra c hip high-voltage mixed-signal ic ?1999~2008 34 mp specifications p ower -d own s equence to prevent the charge stored in capacitor c l causing abnormal residue horizontal line on display when v dd is switched off, use reset mode to enable the built-in charge draining circuit to discharge these external capacitors. f igure 9: reference power-down sequence figure 10: power off-on sequence 10 s < t 1 < 10 ms t f < 10 ms v dd2/3 2.5v v dd 1.8v v dd2/3 v dd either v dd or v dd2/3 may be turned on first. t wait > 10ms v dd < 0.1v reset command turn off the power wait ~1 ms
uc1701 x 65x132 stn controller-drivers revision a1.0 35 s ample c ommand s equences for p ower m anagement the following tables are examples of command sequence for power-up, power-down and display on/off operations. these are only to demonstrate some ? typical, generic ? scenarios. designers are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences are for their specific design needs. c/d the type of the interface cycle. it can be either command (0) or data (1) w/r the direction of data flow of the cycle. it can be either write (0) or read (1). type r equired: these items are required c ustomized: these items are not necessary if customer parameters are the same as default a dvanced: we recommend new users to skip these commands and use default values. o ptional: these commands depend on what users want to do. p ower -u p type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r ? ? ? ? ? ? ? ? ? ? automatic power-on reset. wait ~5ms after v dd is on 1 1 1 1 1 0 1 0 a 0 0 1 0 0 1 0 0 1 1 set adv. program control 0 set wrap around enable c 0 0 1 0 1 0 0 0 0 # set seg direction c 0 0 1 1 0 0 # ? ? ? set com direction set up lcd format specific parameters, mx, my, etc. c 0 0 1 0 1 0 0 0 1 # set lcd bias ratio r 0 0 0 0 1 0 0 0 0 # 0 # 0 # 0 # 0 # 1 # set electronic volume lcd specific operating voltage setting o 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image r 0 0 1 0 1 0 1 1 1 1 set display enable p ower -d own type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 1 1 0 0 0 1 0 system reset r ? ? ? ? ? ? ? ? ? ? draining capacitor wait ~3ms before v dd off d isplay -off type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 0 1 0 1 1 1 0 set display disable c 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image (image update is optional. data in the ram is retained through the sleep state.) r 0 0 1 0 1 0 1 1 1 1 set display enable
u ltra c hip high-voltage mixed-signal ic ?1999~2008 36 mp specifications esd c onsideration uc1700 series products usually are provided in bare die format to customers. this makes the product particularly sensitive to esd damage during handling and manufacturing process. it is, therefore, highly recommended that lcm makers strictly follow the "jesd 625-a requirements for handling electrostatic- discharge-sensitive (esds) devices" when manufacturing lcm. the following pins in uc1701x require special "esd sensitivity" consideration in particular: machine mode human body mode test mode pins v dd v ss v dd v ss lcd driver 150v 150v 2000v 1500v lcm digital interface 300v 250v 3000v 3000v tst1/2/4 300v 300v 3000v 3000v c b pins 300v 300v 3000v 3000v v lcdin 250v 300v 3000v 3000v lcm hv interface v lcdout 300v 300v 3000v 3000v pwr/gnd -- 300v -- 3000v according to ultrachip's mass production experiences, the esd tolerance conditions are believed to be very stable and can produce high yield in multiple customer sites. however, special care is still required during handling and manufacturing process to avoid unnecessary yield loss due to esd damages.
uc1701 x 65x132 stn controller-drivers revision a1.0 37 a bsolute m aximum r atings in accordance with iec134 - notes 1, 2 and 3. symbol parameter min. max. unit v dd logic supply voltage -0.3 +4.0 v v dd2 lcd generator supply voltage -0.3 +4.0 v v dd3 analog circuit supply voltage -0.3 +4.0 v v dd2/3 -v dd voltage difference between v dd and v dd2/3 -- 1.2 v v lcd lcd generated voltage -0.3 +13.2 v v in / v out any input/output -0.4 v dd + 0.3 v t opr operating temperature range -30 +85 o c t str storage temperature -55 +125 o c notes 1. v dd is based on v ss = 0v 2. stress values listed above may cause permanent damages to the device.
u ltra c hip high-voltage mixed-signal ic ?1999~2008 38 mp specifications s pecifications dc c haracteristics symbol parameter conditions min. typ. max. unit v dd supply for digital circuit 1.65 1.8~3.3 3.6 v v dd2/3 supply for bias & pump 2.4 2.5~3.3 3.6 v v lcd charge pump output v dd2/3 2.4v, 25 o c 11.5 v v d lcd data voltage v dd2/3 2.4v, 25 o c 0.80 1.32 v v il input logic low 0.2v dd v v ih input logic high 0.8v dd v v ol output logic low 0.2v dd v v oh output logic high 0.8v dd v i il input leakage current 1.5 a i sb standby current v dd = v dd2/3 = 3.3v, temp = 85 o c 50 a c in input capacitance 5 10 pf c out output capacitance 5 10 pf r 0(seg) seg output impedance v lcd = 11v 2000 3000 ? r 0(com) com output impedance v lcd = 11v 2000 3000 ? duty=1/65 77 duty=1/49 153 duty=1/33 76 f fr average frame rate duty=1/55 -10% 136 +10% hz p ower c onsumption v dd = 2.7 v, bias ratio = 0b, pm = 32, v lcd = 8.49 v frame rate = 77hz, c l = 330 nf, mux rate = 65, bus mode = 6800, all outputs are open circuit. c b = 2.2 f temperature = 25 o c display pattern conditions typ. max. all-off bus = idle 190 304 2-pixel checker bus = idle 192 308 1-pixel checker bus = idle 203 325 - bus = idle (standby current) - 5
uc1701 x 65x132 stn controller-drivers revision a1.0 39 ac c haracteristics f igure 11: parallel bus timing characteristics (for 8080 mcu) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units setup time t as80 t ah80 cd address hold time 0 5 ? ns setup time t cssa80 t csh80 cs1/cs0 chip select hold time 5 5 ? ns read t cy80 cycle time write 120 80 ? ns t pwr80 wr1 read t pww80 wr0 pulse width write 60 40 ? ns read t hpw80 wr0, wr1 high pulse width write 60 40 ? ns setup time t ds80 t dh80 d7~d0 data hold time 30 0 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 20 60 ? ns (1.65v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units setup time t as80 t ah80 cd address hold time 0 0 ? ns setup time t cssa80 t csh80 cs1/cs0 chip select hold time 5 5 ? ns read t cy80 system cycle time write 240 160 ? ns t pwr80 wr1 read t pww80 wr0 pulse width write 120 80 ? ns read t hpw80 wr0, wr1 high pulse width write 120 80 ? ns setup time t ds80 t dh80 d7~d0 data hold time 60 0 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 50 100 ? ns cd t as80 t ah80 cs0 cs1 t cssa80 t cy80 t csh80 t pwr80 , t pww80 t hpw80 wr0 wr1 t ds80 t dh80 write d[7:0] t acc80 t od80 read d[7:0]
u ltra c hip high-voltage mixed-signal ic ?1999~2008 40 mp specifications f igure 12: parallel bus timing characteristics (for 6800 mcu) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units setup time t as68 t ah68 cd address hold time 0 0 ? ns setup time t cssa68 t csh68 cs1/cs0 chip select hold time 5 5 ? ns read t cy68 system cycle time write 120 80 ? ns t pwr68 read t pww68 wr1 pulse width write 60 40 ? ns read t hpw68 high pulse width write 60 40 ? ns setup time t ds68 t dh68 d7~d0 data hold time 30 0 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 50 60 ? ns (1.65v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units setup time t as68 t ah68 cd address hold time 0 0 ? ns setup time t cssa68 t csh68 cs1/cs0 chip select hold time 5 5 ns read t cy68 cycle time write 240 160 ? ns t pwr68 read t pww68 wr1 pulse width write 120 80 ? ns read t hpw68 high pulse width write 120 80 ? ns setup time t ds68 t dh68 d7~d0 data hold time 60 0 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 100 100 ? ns cd t as68 t ah68 cs0 cs1 t cssa68 t cy68 t csh68 t pwr68 , t pww68 t hpw68 wr1 t ds68 t dh68 write d[7:0] t acc68 t od68 read d[7:0]
uc1701 x 65x132 stn controller-drivers revision a1.0 41 f igure 13: serial bus timing characteristics (for s8) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t ass8 setup time t ahs8 cd address hold time 0 0 ? ns t cssas8 setup time t cshs8 cs1/cs0 chip select hold time 5 5 ? ns read t cys8 cycle time write 100 30 ? ns read t lpws8 low pulse width write 50 15 ? ns read t hpws8 sck high pulse width write 50 15 ? ns t dss8 setup time t dhs8 sda data hold time 12 0 ? ns (1.65v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t ass8 setup time 0 t ahs8 cd address hold time 0 ? ns t cssas8 setup time 10 t cshs8 cs1/cs0 chip select hold time 10 ? ns read 130 t cys8 cycle time write 60 ? ns read 65 t lpws8 low pulse width write 30 ? ns read 65 t hpws8 sck high pulse width write 30 ? ns t dss8 setup time 24 t dhs8 sda data hold time 0 ? ns cd cs0 sck sda write cs1 t ass8 t ahs8 t cssas8 t cys8 t lpws8 t hpws8 t cshs8 t dss8 t dhs8
u ltra c hip high-voltage mixed-signal ic ?1999~2008 42 mp specifications rst t rw wr[1:0] t rd f igure 14: reset characteristics (1.65v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t rw rst reset low pulse width 3 ? s t rd rst, wr reset to wr pulse delay 6 ? ms
uc1701 x 65x132 stn controller-drivers revision a1.0 43 p hysical d imensions d ie s ize : 4850 m x 660 m 40 m d ie t hickness : 400 m 20 m b ump height : 15 m 3 m (h max ? h min ) within die 2 m b ump s ize : 15 m x 138.5 m 2 m (typ.) b ump p itch : 27 m b ump g ap : 12 m c oordinate origin : chip center p ad reference : pad center (drawing and coordinates are for the circuit/bump view.)
u ltra c hip high-voltage mixed-signal ic ?1999~2008 44 mp specifications a lignment m ark i nformation s hape of the alignment mark : t op m etal and p assivation : f or p rocess c ross -s ection metal3 / 9k ? sio2 / 5k ? sin / 7k ? n ote : alignment mark is on metal3 under passivation. the ?+? mark is symmetric both horizontally and vertically. c oordinates : d-left mark (+) d-right mark (+) x y x y 1 -1984.5 -149.5 1969.5 -149.5 2 -1969.5 -184.5 1984.5 -184.5 3 -1994.5 -159.5 1959.5 -159.5 4 -1959.5 -174.5 1994.5 -174.5 c -1977 -167 1977 -167 mark mark (0,0) d-left d-right 1 2 3 4 c
uc1701 x 65x132 stn controller-drivers revision a1.0 45 p ad c oordinates # pad x y w h 1 com54 -2363 -227.75 15 138.5 2 com55 -2336 -227.75 15 138.5 3 com56 -2309 -227.75 15 138.5 4 com57 -2282 -227.75 15 138.5 5 com58 -2255 -227.75 15 138.5 6 com59 -2228 -227.75 15 138.5 7 com60 -2201 -227.75 15 138.5 8 com61 -2174 -227.75 15 138.5 9 com62 -2147 -227.75 15 138.5 10 com63 -2120 -227.75 15 138.5 11 com64 -2093 -227.75 15 138.5 12 cic -2066 -227.75 15 138.5 13 tst4 -1970 -274.5 50 45 14 cs0 -1905 -274.5 50 45 15 rst -1840 -274.5 50 45 16 cd -1775 -274.5 50 45 17 wr0 -1710 -274.5 50 45 18 wr1 -1645 -274.5 50 45 19 vddx -1580 -274.5 50 45 20 d0 -1515 -274.5 50 45 21 d1 -1450 -274.5 50 45 22 d2 -1385 -274.5 50 45 23 d3 -1320 -274.5 50 45 24 d4 -1255 -274.5 50 45 25 d5 -1190 -274.5 50 45 26 d6 -1125 -274.5 50 45 27 d7 -1060 -274.5 50 45 28 vdd1 -995 -274.5 50 45 29 vdd1 -930 -274.5 50 45 30 vdd2 -865 -274.5 50 45 31 vdd2 -800 -274.5 50 45 32 vdd2 -735 -274.5 50 45 33 vdd3 -670 -274.5 50 45 34 vss1 -605 -274.5 50 45 35 vss1 -540 -274.5 50 45 36 vss2 -475 -274.5 50 45 37 vss2 -410 -274.5 50 45 38 vss2 -345 -274.5 50 45 39 vss2 -280 -274.5 50 45 40 vb1+ -215 -274.5 50 45 41 vb1+ -150 -274.5 50 45 42 dummy -85 -274.5 50 45 43 vb0+ -20 -274.5 50 45 44 vb0+ 45 -274.5 50 45 45 vb0- 110 -274.5 50 45 46 vb0- 175 -274.5 50 45 47 dummy 240 -274.5 50 45 48 vb1- 305 -274.5 50 45 49 vb1- 370 -274.5 50 45 50 vb1+ 435 -274.5 50 45 51 vb1+ 500 -274.5 50 45 52 vlcdin 565 -274.5 50 45 53 vlcdin 630 -274.5 50 45 54 vlcdout 695 -274.5 50 45 55 vlcdout 760 -274.5 50 45 56 dummy 820 -274.5 45 45 57 dummy 875 -274.5 45 45 58 dummy 930 -274.5 45 45 # pad x y w h 59 dummy 985 -274.5 45 45 60 dummy 1040 -274.5 45 45 61 dummy 1095 -274.5 45 45 62 dummy 1150 -274.5 45 45 63 dummy 1205 -274.5 45 45 64 dummy 1260 -274.5 45 45 65 tst2 1320 -274.5 50 45 66 vssl 1385 -274.5 50 45 67 vddx 1450 -274.5 50 45 68 bm0 1515 -274.5 50 45 69 bm1 1580 -274.5 50 45 70 dt1 1645 -274.5 50 45 71 vssx 1710 -274.5 50 45 72 dt2 1775 -274.5 50 45 73 vdd1 1840 -274.5 50 45 74 vdd2 1905 -274.5 50 45 75 vdd3 1970 -274.5 50 45 76 com32 2066 -227.75 15 138.5 77 com31 2093 -227.75 15 138.5 78 com30 2120 -227.75 15 138.5 79 com29 2147 -227.75 15 138.5 80 com28 2174 -227.75 15 138.5 81 com27 2201 -227.75 15 138.5 82 com26 2228 -227.75 15 138.5 83 com25 2255 -227.75 15 138.5 84 com24 2282 -227.75 15 138.5 85 com23 2309 -227.75 15 138.5 86 com22 2336 -227.75 15 138.5 87 com21 2363 -227.75 15 138.5 88 com20 2363 227.75 15 138.5 89 com19 2336 227.75 15 138.5 90 com18 2309 227.75 15 138.5 91 com17 2282 227.75 15 138.5 92 com16 2255 227.75 15 138.5 93 com15 2228 227.75 15 138.5 94 com14 2201 227.75 15 138.5 95 com13 2174 227.75 15 138.5 96 com12 2147 227.75 15 138.5 97 com11 2120 227.75 15 138.5 98 com10 2093 227.75 15 138.5 99 com9 2066 227.75 15 138.5 100 com8 2039 227.75 15 138.5 101 com7 2012 227.75 15 138.5 102 com6 1985 227.75 15 138.5 103 com5 1958 227.75 15 138.5 104 com4 1931 227.75 15 138.5 105 com3 1904 227.75 15 138.5 106 com2 1877 227.75 15 138.5 107 com1 1850 227.75 15 138.5 108 cic 1823 227.75 15 138.5 109 seg1 1768.5 227.75 15 138.5 110 seg2 1741.5 227.75 15 138.5 111 seg3 1714.5 227.75 15 138.5 112 seg4 1687.5 227.75 15 138.5 113 seg5 1660.5 227.75 15 138.5 114 seg6 1633.5 227.75 15 138.5 115 seg7 1606.5 227.75 15 138.5 116 seg8 1579.5 227.75 15 138.5 # pad x y w h 117 seg9 1552.5 227.75 15 138.5 118 seg10 1525.5 227.75 15 138.5 119 seg11 1498.5 227.75 15 138.5 120 seg12 1471.5 227.75 15 138.5 121 seg13 1444.5 227.75 15 138.5 122 seg14 1417.5 227.75 15 138.5 123 seg15 1390.5 227.75 15 138.5 124 seg16 1363.5 227.75 15 138.5 125 seg17 1336.5 227.75 15 138.5 126 seg18 1309.5 227.75 15 138.5 127 seg19 1282.5 227.75 15 138.5 128 seg20 1255.5 227.75 15 138.5 129 seg21 1228.5 227.75 15 138.5 130 seg22 1201.5 227.75 15 138.5 131 seg23 1174.5 227.75 15 138.5 132 seg24 1147.5 227.75 15 138.5 133 seg25 1120.5 227.75 15 138.5 134 seg26 1093.5 227.75 15 138.5 135 seg27 1066.5 227.75 15 138.5 136 seg28 1039.5 227.75 15 138.5 137 seg29 1012.5 227.75 15 138.5 138 seg30 985.5 227.75 15 138.5 139 seg31 958.5 227.75 15 138.5 140 seg32 931.5 227.75 15 138.5 141 seg33 904.5 227.75 15 138.5 142 seg34 877.5 227.75 15 138.5 143 seg35 850.5 227.75 15 138.5 144 seg36 823.5 227.75 15 138.5 145 seg37 796.5 227.75 15 138.5 146 seg38 769.5 227.75 15 138.5 147 seg39 742.5 227.75 15 138.5 148 seg40 715.5 227.75 15 138.5 149 seg41 688.5 227.75 15 138.5 150 seg42 661.5 227.75 15 138.5 151 seg43 634.5 227.75 15 138.5 152 seg44 607.5 227.75 15 138.5 153 seg45 580.5 227.75 15 138.5 154 seg46 553.5 227.75 15 138.5 155 seg47 526.5 227.75 15 138.5 156 seg48 499.5 227.75 15 138.5 157 seg49 472.5 227.75 15 138.5 158 seg50 445.5 227.75 15 138.5 159 seg51 418.5 227.75 15 138.5 160 seg52 391.5 227.75 15 138.5 161 seg53 364.5 227.75 15 138.5 162 seg54 337.5 227.75 15 138.5 163 seg55 310.5 227.75 15 138.5 164 seg56 283.5 227.75 15 138.5 165 seg57 256.5 227.75 15 138.5 166 seg58 229.5 227.75 15 138.5 167 seg59 202.5 227.75 15 138.5 168 seg60 175.5 227.75 15 138.5 169 seg61 148.5 227.75 15 138.5 170 seg62 121.5 227.75 15 138.5 171 seg63 94.5 227.75 15 138.5 172 seg64 67.5 227.75 15 138.5 173 seg65 40.5 227.75 15 138.5 174 seg66 13.5 227.75 15 138.5
u ltra c hip high-voltage mixed-signal ic ?1999~2008 46 mp specifications # pad x y w h 175 seg67 -13.5 227.75 15 138.5 176 seg68 -40.5 227.75 15 138.5 177 seg69 -67.5 227.75 15 138.5 178 seg70 -94.5 227.75 15 138.5 179 seg71 -121.5 227.75 15 138.5 180 seg72 -148.5 227.75 15 138.5 181 seg73 -175.5 227.75 15 138.5 182 seg74 -202.5 227.75 15 138.5 183 seg75 -229.5 227.75 15 138.5 184 seg76 -256.5 227.75 15 138.5 185 seg77 -283.5 227.75 15 138.5 186 seg78 -310.5 227.75 15 138.5 187 seg79 -337.5 227.75 15 138.5 188 seg80 -364.5 227.75 15 138.5 189 seg81 -391.5 227.75 15 138.5 190 seg82 -418.5 227.75 15 138.5 191 seg83 -445.5 227.75 15 138.5 192 seg84 -472.5 227.75 15 138.5 193 seg85 -499.5 227.75 15 138.5 194 seg86 -526.5 227.75 15 138.5 195 seg87 -553.5 227.75 15 138.5 196 seg88 -580.5 227.75 15 138.5 197 seg89 -607.5 227.75 15 138.5 198 seg90 -634.5 227.75 15 138.5 199 seg91 -661.5 227.75 15 138.5 200 seg92 -688.5 227.75 15 138.5 201 seg93 -715.5 227.75 15 138.5 202 seg94 -742.5 227.75 15 138.5 203 seg95 -769.5 227.75 15 138.5 204 seg96 -796.5 227.75 15 138.5 205 seg97 -823.5 227.75 15 138.5 206 seg98 -850.5 227.75 15 138.5 207 seg99 -877.5 227.75 15 138.5 208 seg100 -904.5 227.75 15 138.5 209 seg101 -931.5 227.75 15 138.5 210 seg102 -958.5 227.75 15 138.5 211 seg103 -985.5 227.75 15 138.5 212 seg104 -1012.5 227.75 15 138.5 213 seg105 -1039.5 227.75 15 138.5 214 seg106 -1066.5 227.75 15 138.5 215 seg107 -1093.5 227.75 15 138.5 216 seg108 -1120.5 227.75 15 138.5 217 seg109 -1147.5 227.75 15 138.5 218 seg110 -1174.5 227.75 15 138.5 219 seg111 -1201.5 227.75 15 138.5 220 seg112 -1228.5 227.75 15 138.5 221 seg113 -1255.5 227.75 15 138.5 222 seg114 -1282.5 227.75 15 138.5 223 seg115 -1309.5 227.75 15 138.5 224 seg116 -1336.5 227.75 15 138.5 225 seg117 -1363.5 227.75 15 138.5 226 seg118 -1390.5 227.75 15 138.5 227 seg119 -1417.5 227.75 15 138.5 228 seg120 -1444.5 227.75 15 138.5 229 seg121 -1471.5 227.75 15 138.5 230 seg122 -1498.5 227.75 15 138.5 231 seg123 -1525.5 227.75 15 138.5 232 seg124 -1552.5 227.75 15 138.5 233 seg125 -1579.5 227.75 15 138.5 234 seg126 -1606.5 227.75 15 138.5 # pad x y w h 235 seg127 -1633.5 227.75 15 138.5 236 seg128 -1660.5 227.75 15 138.5 237 seg129 -1687.5 227.75 15 138.5 238 seg130 -1714.5 227.75 15 138.5 239 seg131 -1741.5 227.75 15 138.5 240 seg132 -1768.5 227.75 15 138.5 241 com33 -1823 227.75 15 138.5 242 com34 -1850 227.75 15 138.5 243 com35 -1877 227.75 15 138.5 244 com36 -1904 227.75 15 138.5 245 com37 -1931 227.75 15 138.5 246 com38 -1958 227.75 15 138.5 247 com39 -1985 227.75 15 138.5 248 com40 -2012 227.75 15 138.5 249 com41 -2039 227.75 15 138.5 250 com42 -2066 227.75 15 138.5 251 com43 -2093 227.75 15 138.5 252 com44 -2120 227.75 15 138.5 253 com45 -2147 227.75 15 138.5 254 com46 -2174 227.75 15 138.5 255 com47 -2201 227.75 15 138.5 256 com48 -2228 227.75 15 138.5 257 com49 -2255 227.75 15 138.5 258 com50 -2282 227.75 15 138.5 259 com51 -2309 227.75 15 138.5 260 com52 -2336 227.75 15 138.5 261 com53 -2363 227.75 15 138.5
uc1701 x 65x132 stn controller-drivers revision a1.0 47 t ray i nformation mm +/-0.1 n/a n/a unit angle general tolerance dimension roughness unless otherwise specified l2 l3 l1 t l2 l3 l1 p1 p2 p1 p2 t 7x22=154 20-199x34-24 sx z x px 1 0 z sy s 1.94 1.77 y py 1 0
u ltra c hip high-voltage mixed-signal ic ?1999~2008 48 mp specifications r evision h istory revision contents date of rev. 0.6 first release jul. 29, 2008 (1) a new register, apc, is added. (section ?control registers?, page 10) (2) command ?set advanced program control? is split into 2 commands. (section ?command table?, - (25)(26), page 12; ?command description? ? (25)(26), page 17) (3) the sample codes for power-up are updated. (section ?sample command sequences for power management?, page 34) 0.7 (4) the tray drawing is updated. (section ?tray information?, page 46) aug. 8, 2008 (1) v lcd data are updated. (section ?v lcd quick reference?, page 19) (2) the description on mux-rate is updated. (section ?lcd display controls? ? clock & timing generator, page 21) (3) power consumption data present. (section ?specifications? ? power consumption, page 37) 0.8 (4) some ac timings are adjusted. (section ?ac characteristics?, pp 38~40) aug. 27, 2008 (1) the setting of wr[1:0] in s8 mode is updated: 0 ? ? (section ?pin description? ? wr1~0, page 7; ?host interface?, page 25) (2) power up and enter/exit sleep mode sequences are updated. (section ?reset & power management?, page 32) 1.0 (3) esd data are corrected. (section ?esd consideration?, page 36) nov. 7, 2008

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